Browsing by Subject "H03M 13/13"

Now showing items 1-14 of 14

    • Asymmetric error correction and flash-memory rewriting using polar codes 
      En Gad, Eyal; Li, Yue; Kliewer, Joerg; Langberg, Michael; Jiang, Anxiao; Bruck, Jehoshua (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2019-08-13)
      Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and ...
    • Joint rewriting and error correction in write-once memories 
      Jiang, Anxiao; Li, Yue; En Gad, Eyal; Langberg, Michael; Bruck, Jehoshua (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-04-17)
      Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2015-08-18)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2021-03-16)
      A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2020-04-07)
      A method and system for decoding low density parity check ("LDPC") codes. A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low Density Parity Check Decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 6/21/2022)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-10-08)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran K.; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-04-09)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...
    • Low density parity check decoder for regular LDPC codes 
      Gunnam, Kiran K.; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-01-22)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder for regular LDPC codes 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2014-02-18)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Rank-modulation rewriting codes for flash memories 
      Jiang, Anxiao; En Gad, Eyal; Bruck, Jehoshua; Yaakobi, Eitan (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2015-07-21)
      Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. ...
    • Rank-modulation rewriting codes for flash memories 
      Jiang, Anxiao; En Gad, Eyal; Bruck, Jehoshua; Yaakobi, Eitan (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-03-13)
      Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. ...