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    Pseudo-dynamic differential flip-flop

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    6140845.pdf (389.2Kb)
    Date
    2000-10-31
    Author
    Benachour, Abdelaziz
    Metadata
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    Abstract
    A differential flip-flop having reduced circuit complexity, clock loading, and power consumption. The circuit is particularly well adapted for systems requiring high-speed differential flip-flops. The proposed flip-flop uses the parasitic capacitors associated with circuit nodes to dynamically store information. The differential flip-flop uses only one current source, as opposed to the two typically required by its conventional counterpart, saving fifty percent of the total power requirement. This power saving is a tremendous advantage at high frequencies, since current must be high to ensure high-speed operation of the transistors in the circuit. Furthermore, the new flip-flop presents a significantly reduced (fifty percent) load to the clock driver, thus further enhancing the power performance of the systems in which it is used.
    URI
    https://hdl.handle.net/1969.1/176648
    Subject
    327/57
    327/199
    327/202
    327/212
    327/215
    H03K 3/012
    H03K 3/356043
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    • Texas A&M University Patents
    Citation
    Benachour, Abdelaziz (2000). Pseudo-dynamic differential flip-flop. United States. Patent and Trademark Office; Texas A&M University. Libraries. Available electronically from https : / /hdl .handle .net /1969 .1 /176648.

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