Pseudo-dynamic differential flip-flop

Abstract

A differential flip-flop having reduced circuit complexity, clock loading, and power consumption. The circuit is particularly well adapted for systems requiring high-speed differential flip-flops. The proposed flip-flop uses the parasitic capacitors associated with circuit nodes to dynamically store information. The differential flip-flop uses only one current source, as opposed to the two typically required by its conventional counterpart, saving fifty percent of the total power requirement. This power saving is a tremendous advantage at high frequencies, since current must be high to ensure high-speed operation of the transistors in the circuit. Furthermore, the new flip-flop presents a significantly reduced (fifty percent) load to the clock driver, thus further enhancing the power performance of the systems in which it is used.