Browsing by Author "Choi, Gwan S."

Now showing items 1-20 of 25

    • Accelerating Communication in On-Chip Interconnection Networks 
      Ahn, Minseon (2012-07-16)
      Due to the ever-shrinking feature size in CMOS process technology, it is expected that future chip multiprocessors (CMPs) will have hundreds or thousands of processing cores. To support a massively large number of cores, ...
    • Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation 
      Gunnam, Kiran Kumar (2009-05-15)
      The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and ...
    • Auxiliary Loss Weighting for Robust Multi-Modal Sensor Fusion with Deep Neural Networks 
      Li, Yang (2019-04-08)
      The major focus of this research is on sensor fusion. Sensor fusion means to combine multiple sensory input or data from different source such that the performance is better than the best performance would be when those ...
    • Communication synthesis of networks-on-chip (NoC) 
      Bhojwani, Praveen Sunder (2009-05-15)
      The emergence of networks-on-chip (NoC) as the communication infrastructure solution for complex multi-core SoCs presents communication synthesis challenges. This dissertation addresses the design and run-time management ...
    • Design and analysis of a 3-dimensional cluster multicomputer architecture using optical interconnection for petaFLOP computing 
      Okorafor, Ekpe Apia (Texas A&M University, 2007-04-25)
      In this dissertation, the design and analyses of an extremely scalable distributed multicomputer architecture, using optical interconnects, that has the potential to deliver in the order of petaFLOP performance is presented ...
    • Determining the Impact of Concrete Roadways on Gamma Ray Background Readings for Radiation Portal Monitoring Systems 
      Ryan, Christopher Michael (2012-07-16)
      The dissolution of the Soviet Union coupled with the growing sophistication of international terror organizations has brought about a desire to ensure that a sound infrastructure exists to interdict smuggled nuclear material ...
    • Dynamic Power Management of High Performance Network on Chip 
      Mandal, Suman Kalyan (2012-02-14)
      With increased density of modern System on Chip(SoC) communication between nodes has become a major problem. Network on Chip is a novel on chip communication paradigm to solve this by using highly scalable and efficient ...
    • Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy 
      Chang, Sanghoan (2009-05-15)
      The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. ...
    • Hardware Solutions for Next Generation of Telecommunication Systems Physical Layer Implementation 
      Rohani, Ehsan (2017-12-11)
      In telecommunication systems the goal is to increase the throughput of data communication. Multiple input and multiple output antennas (MIMO) can be used to increase the SNR of the system and as the result increase the ...
    • HW/SW Codesign and Design, Evaluation of Software Framework for AcENoCs : An FPGA-Accelerated NoC Emulation Platform 
      Pai, Vinayak (2011-02-22)
      Majority of the modern day compute intensive applications are heterogeneous in nature. To support their ever increasing computational requirements, present day System-on-Chip (SoC) architectures have adapted multicore ...
    • Hybrid Verification for Analog and Mixed-signal Circuits 
      Zheng, Qingran (2017-12-08)
      With increasing design complexity and reliability requirements, analog and mixedsignal (AMS) verification manifests itself as a key bottleneck. While formal methods and machine learning have been proposed for AMS verification, ...
    • Large-Scale Simulation of Neural Networks with Biophysically Accurate Models on Graphics Processors 
      Wang, Mingchao (2012-07-16)
      Efficient simulation of large-scale mammalian brain models provides a crucial computational means for understanding complex brain functions and neuronal dynamics. However, such tasks are hindered by significant computational ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2015-08-18)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2018-11-27)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2021-03-16)
      A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2020-04-07)
      A method and system for decoding low density parity check ("LDPC") codes. A method and system for decoding low density parity check ("LDPC") codes. An LDPC code decoder includes decoding circuitry configured to process ...
    • Low Density Parity Check Decoder 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 6/21/2022)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran Kumar; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-10-08)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...
    • Low density parity check decoder for irregular LDPC codes 
      Gunnam, Kiran K.; Choi, Gwan S. (United States. Patent and Trademark Office; Texas A&M University. Libraries, 2013-04-09)
      A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density ...