Enhancing the Hardware-Based Advanced Encryption Standard Implementation for Optimized Performance in Cyber-Physical Systems

Abstract

Cyber-Physical Systems play a pivotal role in critical infrastructures but face distinct security challenges. Traditional software-based security measures often disregard to account for the resource limitations that these systems encounter. Field Programmable Gate Arrays offer a solution, enabling hardware-based cryptographic implementations to enhance security. This study delves into the design and analysis of optimized variants of cryptographic encryption implemented on hardware, shedding light on design methodologies and optimization techniques. Our research includes physical verification, rendering the encryption core readily applicable to be deployed in existing systems. Notably, this study goes beyond the existing research landscape, where the focus on specific metrics often neglects the holistic perspective. Our performance analysis, with a particular emphasis on throughput, undergoes rigorous scrutiny and provides a comprehensive view previously unexplored. This work significantly contributes to enhancing security by introducing efficient hardware-based cryptographic solutions and advancing the field with a comprehensive performance analysis.