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An Analysis of the Practicality of Hardware Acceleration for Lightweight Block Ciphers in a Field Programmable Gate Array
Abstract
The Internet of Things (IoT) is prompting a rapid shift in the way that encryption is performed by resource-constrained devices. Embedded devices are unable to implement the same cipher algorithms that general-purpose computers use. This project aims to examine practical considerations for implementing lightweight block cipher algorithms in a field programmable gate array (FPGA) for the purpose of hardware acceleration of encryption for constrained devices. To do this, four block cipher algorithms were implemented. Three lightweight ciphers from ISO 29192-2 (Present, Clefia, and Lea) and the Advanced Encryption Standard (AES) were selected. In addition, the necessary logic to have them interface with another device such as a microcontroller was implemented. The effectiveness of the serial communication between the FPGA and microcontroller is examined using metrics such as data transmit speed and the maximum feasible clock speed. The performance is analyzed using metrics such as computation time, encryption throughput, power consumption, efficiency, and the number of logic units used.
Subject
Internet of ThingsConstrained Devices
Hardware Acceleration
FPGA
Lightweight Cryptography
Block Cipher
Collections
Citation
Neal, Zachary M (2023). An Analysis of the Practicality of Hardware Acceleration for Lightweight Block Ciphers in a Field Programmable Gate Array. Master's thesis, Texas A&M University. Available electronically from https : / /hdl .handle .net /1969 .1 /203011.