| dc.description.abstract | The benefits of Moore’s Law are waning and effects of Dennard Scaling are ending, resulting in modern computing designs improving performance through new and creative designs. These designs target modern performance barriers but introduce new threat vectors that bad actors may exploit to compromise the design and manufacturing process.
Server and database computing system performance can improve by increasing machines’ ability to facilitate fast instruction memory accesses to overcome the front-end bottleneck, generally through prefetching. Prefetching is a technique to predict future instruction accesses and place them in the caches before use. In this dissertation, we propose a framework for combining pre-existing hardware prefetchers into a single composite prefetcher to target different instruction stream behaviors during execution.
Software prefetching has recently resurfaced as an alternative to hardware prefetching. While promising, recent proposals do not model industry-standard front-ends in their evaluation. In this dissertation we identify the potential states the front-end can be in and software instruction prefetching’s effect on the front-end that degrades performance.
Industry is moving toward chiplet-based designs, which divide systems into chiplets and integrate them onto an interposer via 2.5D integration. This design flow disaggregates the manufacturing and design process between multiple vendors with varying trustworthiness, increasing hardware Trojans’ potential insertion and threat. These systems rely on cache coherence for data communication, making coherence an attractive target. Trojan attacks exploiting coherence can modify data in memory that the compromised chiplet never touched or owned. Further, the Trojan need not be physically between the victim and the memory controller to attack a victim’s memory transactions. This dissertation explores the fundamental coherence attack vectors possible in chiplet-based systems. Further, we provide an example Trojan implementation capable of directly modifying victim data in memory without disrupting system execution.
To counter coherence threats, we propose a defense mechanism leveraging an active interposer to produce a generic, secure-by-construction platform forming a physical root of trust for 2.5D systems. The scheme has limited overhead, restricted to the active interposer, allowing the chiplets and the coherence system to remain unmodified. This scheme prevents coherence attacks with little impact on system performance, ∼4%, which reduces as workloads increase, ensuring scalability. | |
