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dc.contributor.advisorHarris, Harlan R
dc.creatorYamamoto, Alexandre Yasuo
dc.date.accessioned2020-09-11T19:28:37Z
dc.date.available2021-12-01T08:42:56Z
dc.date.created2019-12
dc.date.issued2019-08-22
dc.date.submittedDecember 2019
dc.identifier.urihttps://hdl.handle.net/1969.1/189232
dc.description.abstractMemristors are the predicted fourth fundamental passive element of circuits, connecting a previously missing relationship between charge q and flux-linkage φ. It was first fabricated by a team led by Stanley Williams in 2008 and since many examples have been fabricated, but there is still much debate over how to properly model these devices, what is the physical mechanism for their behavior and even whether or not current examples can be considered the theoretical Memristor predicted by Leon Chua in 1971. This dissertation shows that barriers preventing injection of charges to the switching medium are likely the cause of exponential terms in model, and this phenomenological cause for the differences found between manufactured devices and the theoretical device can be simply translated by diodes in series with an "ideal" Memristor. These non-idealities can be modeled by devices familiar to circuit designer such as diodes, and by using common tools such as SPICE, an effective model is provided for simulation of Memristors. To try and clear the confusion over what an ideal Memristor is, a new unit of memristance is proposed, being named after Leon Chua: the Chua [Ch], representing the SI units of Ω/C. It is shown that this new way of describing Memristors by their own merit is valid and derives from the same reciprocity that suggested the existence of the device in the first place, being validated against several fabricated examples. This theory also explains some difficulties in measuring these devices, namely the fact that measurement and forming of the memristance are not completely independent and the fact that there is an inverse square dependency with the area; effectively explaining why memristive devices were found only when process nodes shrunk enough that the effects were more obvious. Finally, this work proposes a structure that is simultaneously a HEMT and a Memristor, and cannot simply be explained by an association of one of each device; this is because the threshold voltage of the transistor appears to change proportionally to the state variable of the Memristor, effectively correlating the devices and causing an amplification of the change in resistance of the memristor. This fact enables the creation of a memristive synapse that could be used in future neuromorphic circuitry, being more efficient than currently proposed 1T1M circuits.en
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectMemristoren
dc.subjectMemristor Engineeringen
dc.subjectNeuromorphic Computingen
dc.subjectReRAMen
dc.subjectMemristor Characterizationen
dc.subjectMemristor Modelingen
dc.titleMemristor Engineering: Modeling, Fabrication, and Characterizationen
dc.typeThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameDoctor of Philosophyen
thesis.degree.levelDoctoralen
dc.contributor.committeeMemberKameoka, Jun
dc.contributor.committeeMemberLi, Peng
dc.contributor.committeeMemberZubairy, Muhammad S
dc.type.materialtexten
dc.date.updated2020-09-11T19:28:38Z
local.embargo.terms2021-12-01
local.etdauthor.orcid0000-0003-3695-3738


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