Low-Dropout Regulator with Transient Response Enhancement Based on a Bang-Bang Technique

Abstract

The concept full chip integration of circuits has gained traction over the years with the push towards system-on-chip (SoC) designs which serve the niche for portable, low-power devices from the handheld category to wearables. As such, there is a growing trend towards the integration of Linear Dropout (LDO) regulators, which are a pivotal part of the power systems in such devices. However, removing the large output capacitor in LDOs to allow for full chip integration comes at a cost as it leads to higher overshoots and undershoots during load transients and degrades AC stability. This work presents the design of an output capacitor-less LDO regulator which uses a bang-bang technique for reduction of overshoot and undershoot during load transients. This technique provides an alternate faster loop for transient compensation while keeping power consumption low. Also, an error amplifier which uses a combination of miller compensation and quality factor reduction technique is also employed to ensure AC stability across the load range. At an output voltage of 1.1 V, the regulator proves to be stable at loads ranging from 0-100 mA with a 100 pF load capacitance. A quiescent current consumption of 16.5 uA and a dropout voltage of 200 mV ensure a high power efficiency of 84.6%. From simulations, the worst case overshoot and undershoot of the regulator are 108 mV and 88 mV respectively with a 1% settling time of 3.2 us and a load regulation of 0.11 mV/mA. The regulator is designed and implemented fully on-chip in IBM 130nm technology.