Integrated Circuit Design for Silicon Photonics Interconnects

Abstract

For next generation interconnects which implement in datacenter and high-performance computing system, silicon photonic interconnect provides a high bandwidth, low power efficiency solution. Optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and high bandwidth density via wavelength division multiplexing. This paper presents a multi-channel hybrid-integrated photonic receiver based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. When tested with a waveguide photodetector with 0.45A/W responsivity, the receiver achieves -8.0 dBm OMA sensitivity at a BER=10-12 with a jitter tolerance corner frequency near 20MHz and a per-channel power consumption of 17mW including amortized clocking power. In order to stabilize the microring drop filter resonance wavelength, a peak-detector-based thermal tuning loop is implemented with a 0.7nm range at 43μW/GHz efficiency. Mach–Zehnder-based modulator provides a high bandwidth, high linearity, good thermal insensitivity solution for silicon photonics transmitters design. This paper presents a 56Gbps PAM4/NRZ reconfigurable Si-photonics transmitter design which consists a 16nm FinFET CMOS transmitter flip-chip bonded to a 130nm SOI Mach–Zehnder modulator. The Mach–Zehnder modulator consists total 14 segmented phase shifter pairs which 5 segments works as LSB and 9 segments works as MSB in order to generate 4-level Pulse-Amplitude Modulation (PAM4) optical signal in optical domain combination. The CMOS transmitter implements 28 push-pull drivers to achieve dual arm, dual differential driving scheme and independently digital control delay lines to achieve delay match between optical and electrical signal propagation. The MZM transmitter achieves 7ps eye-width and 0.963 RLM at 56Gbps data rate.