Device Design Parameterization of III-V Multi-Gate FETs
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The use of group III-V semiconductor materials promise superior performance compared to silicon and can be considered a fundamental paradigm shift away from mature silicon technology. Group III-V semiconductors allow for high power operation, drastically high clock speeds, large breakdown fields, and higher Johnson’s Figure of Merit (JFoM). Due to higher electron drift velocity (vd) of the material set, higher on-state current (Ion) is expected than the one in silicon with reduced supply voltage operation. Additionally, strong spontaneous and piezoelectric polarization properties in the III-Nitrides support tighter carrier confinement with high carrier density in a quantum well channel at the heterointerface. By engineering the III-nitride properties, designing a 3D architecture device includes important physical parameters that must be taken into account to analyze device performance. GaN-based devices are desirable for high RF and high power applications for reducing parasitics and improving efficiency. For this reason, III-nitride semiconductor materials provide the possibility of future integration of GaN fin-based 3D devices. This dissertation describes the experimental realization and electrical analysis of III-V FinFET devices with an AlGaN/GaN heterostructure, called “Multi-Gate Heterostructure Fin Field Effect Transistor (MUG-HFinFET).” Process development begins with the experimental demonstration of a Si-compatible baseline AlGaN/GaN FinFET technology, and an exploration of the impact of physical device design parameters such as fin widths, heights, angles and gate lengths. The ohmic contact formation on AlGaN/GaN heterostructure is realized using different metal stacks while taking into account additional annealing effects and produces comparably low contact resistance to other literature reports. Different fabrication processes to distinguish the impact of the device architectures are demonstrated while simultaneously applying for the integration of high-k dielectric metal-gate stack including surface clean and passivation techniques developed for high quality interfaces and low-leakage performance. After MUG-HFinFET technology is implemented and characterized, the impacts of the device design parameters are benchmarked and shows the guidance to device design at the initial stage forward proper device application. The work concludes by assessing the novel characteristics of AlGaN/GaN heterostructure FinFET devices for 3D device design with distinguished performance. According to the distinguished performance across the device geometries and crystal directions, the benchmarks made in this dissertation will guide future device application development toward an AlGaN/GaN FinFET device design to ensure that a proper device design is achieved.
Suh, Jae Woo (2016). Device Design Parameterization of III-V Multi-Gate FETs. Doctoral dissertation, Texas A & M University. Available electronically from