Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing
MetadataShow full item record
Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time.
path delay test
power supply noise
pseudo functional test
small delay defect
Lahiri, Shayak (2011). Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing. Master's thesis, Texas A&M University. Available electronically from
Showing items related by title, author, creator and subject.
Fault modeling, delay evaluation and path selection for delay test under process variation in nano-scale VLSI circuits Lu, Xiang (Texas A&M University, 2006-04-12)Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, ...
Sadry, Nauzad Erach (Texas A&M University, 2002)Wireless networks have become more prevalent over the last few years. These networks introduce different types of errors, which are due to the unpredictable nature of the wireless channel. The congestion control algorithms ...
Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck–AT, Transition and Small Delay Defect Faults Gill, Arjun (2013-05-01)The ever increasing complexity and size of digital circuits complemented by Deep Sub Micron (DSM) technology trends today pose challenges to the efficient Design For Test (DFT) methodologies. Innovation is required not ...