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dc.contributor.advisorGratz, Paul V.
dc.creatorJagielski, Philip
dc.date.accessioned2011-08-08T22:48:50Z
dc.date.accessioned2011-08-09T01:21:39Z
dc.date.available2011-08-08T22:48:50Z
dc.date.available2011-08-09T01:21:39Z
dc.date.created2011-05
dc.date.issued2011-08-08
dc.date.submittedMay 2011
dc.identifier.urihttp://hdl.handle.net/1969.1/ETD-TAMU-2011-05-9641
dc.description.abstractFor forty years, transistor counts on integrated circuits have doubled roughly every two years, enabling computer architects to double the clock speed of processors. Recently, heat dissipation and power consumption trends have forced chip designers to add larger caches and more cores per chip, instead of increasing clock speed with the extra transistors. This has provided challenges for programmers who wish to continue increasing application performance as though the speed of a uniprocessor had continued doubling. In this characteristic study, we examine the effect of the operating system on a set of parallel benchmarks run on a simulated many-core processor. Past research has shown that the performance of the OS code has a large impact on application performance; however, most studies ignore the OS and focus on the application code. This work will characterize performance bottlenecks and show possible areas that could be improved. We found that resource contention in the kernel was limiting the efficiency of the benchmarks.en
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.subjectSPLASH-2en
dc.subjectM5en
dc.subjectJagielskien
dc.subjectInstruction Flowen
dc.titleCharacterizing Shared Memory Multiprocessor Benchmarks for Future Chip Multiprocessor Architectures Using Instruction Flow Analysisen
thesis.degree.departmentCollege of Engineeringen
thesis.degree.disciplineComputer Engineeringen
thesis.degree.grantorTexas A&M Universityen
thesis.degree.nameBachelor of Scienceen
thesis.degree.levelUndergraduateen
dc.type.genrethesisen
dc.type.materialtexten


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