Communication synthesis for on chip networks

Abstract

The modern day System on Chip (SoC) is made up of a large number of heterogeneous cores with varied communication requirements. On chip networks are the scalable, global interconnection solutions for these explicitly parallel systems. In this thesis, we have analyzed the issues involved in synthesizing these networks and proposed a methodology that will help to arrive at an optimal Network on Chip (NoC) design. Some of the important issues that we consider for synthesis are the quality of service (QoS) requirements of the communicating cores like latency and data rate, the utilization of the network resources and implementation cost issues like area, power and wiring complexity. We have developed a tool-set written mainly in C++, which comprises of an IP clustering engine and an on chip network simulator, to aid the synthesis. We have annotated the models used for communication architecture synthesis with design parameters obtained from gate level synthesis. The tool-set can aid the designer in predicting the various cost parameters and configuring the network on chip architecture for optimal performance. The network simulator, NoCSIM, can be extended to evaluate the performance and feasibility of new and innovative network architectures developed for on chip environment.