A 1.8V 2-2 cascade Sigma-Delta modulator for high speed applications

Abstract

In order to satisfy today's most important requirements of the A/D and D/A converters that are low voltage and high speed operation, a low voltage and high speed circuit solutions for [] modulators are strongly demanding. However, simply reducing the supply voltage and increasing the clock frequency of the [] modulator will introduce severe constraints to the design. In this thesis, a 1.8V 2-2 cascade [] modulator with 1MHz signal bandwidth is realized by employing a modified [] modulator structure which can limit the output swing of the integrator within half the reference voltage. As a result, the supply voltage can be easily reduced without any degradation of the modulator performance. Moreover, the slew rate and bandwidth requirements of the OpAmp are much more alleviated. Also, using only single bit quantizers in each stage, linearity and matching problems are not critical. Circuit level simulation results show a peak SNR of 77.3dB and a peak SNDR of 72.1dB which corresponds to a nearly 13 bit resolution.