Behavioral modeling and digital calibration of pipeline analog to digital converters

Abstract

This research focuses on digital calibration of pipeline analog to digital converters (ADCs) and also modeling of error sources and design parameters of pipeline ADCs. Modern applications such as communications systems require high resolution ADCs at high rates of conversion speed. Pipeline ADCs show great potential for high-speed high-resolution applications. But limited matching property of available process technologies does not permit implementation of high-resolution pipeline ADCs unless a calibration scheme is used. There are two major methods of calibration. The first uses some redundant analog components implemented during the design of the ADC to adjust some of the analog components. These redundant analog components also have limited accuracy and cause some additional problems such as loading and area consumption. Laser trimming of analog components cannot solve the problem due to difficulty of accurate trimming beyond 12-bit. Correcting the component's matching error in digital domain is the second method of calibration. This thesis presents detailed analyses for the possibility of digital correction of the errors due to analog circuitry. As a result an efficient method for the digital calibration method is proposed. This method has the advantage of measuring the required calibration coefficients by sweeping the input voltage through the whole dynamic range.