Abstract
A major problem in circuit design is achieving the maximum performance for a given technology. In the context of logic synthesis and optimization, maximizing performance means reducing the maximum propagation delay from circuit inputs to outputs. As fast turn-around time becomes the major driving force in the electronic industry, there is an increasing need to consider performance aspects during the synthesis process. There are several techniques which improve the circuit speed during the design of a circuit. This work presents one such technique which is applicable to a gate-level description of a multi-level circuit. A combinational optimizer, LOD, which reduces circuit delay with minimal area increase is presented. Heuristics and methods which help in improving the circuit speed with minimal area increase are discussed. Finally, experimental results on IWLS'9I and ISCAS'85 benchmark sets and a comparison with SIS 1.3 will be presented to demonstrate the effectiveness of the proposed technique. Experimental results show that the proposed method results in circuits which have better delay in the majority of cases and better area in all cases than the circuits obtained from delay optimization scripts in SIS 1.3 for a simple library of two input gates.
Munshi, Avinash (1999). A structural approach to delay optimization in combinational circuits. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1999 -THESIS -M86.