An investigation of defect detection using random defect excitation and deterministic defect observation in complex integrated logic circuits

Abstract

Whenever integrated circuits are manufactured, a certain percentage of those circuits will be defective. Defective circuits present problems for both the manufacturers who wish to maintain a good reputation with their customers and the consumers who depend upon the correct operation of the products they buy. Thus, testing must be done to detect which parts are defective so that they are not sold to unwitting consumers. Most current testing methods involve generating test patterns that will detect single stuck-at faults. Unfortunately, however, the single stuck-at fault model cannot adequately describe all of the potential defects that may occur. The requirements for exciting a fault vary depending upon the specific model (stuck-at, bridge, etc.) being used, but the observation of the fault always requires that the erroneous logic value be propagated to a primary output. The proposed new method of automatic test pattern generation involves deterministically observing all of the sites in the circuit as many times as possible while randomly exciting the defects which may occur. This research demonstrates the importance of site observation on the detection of defects and shows some of the inefficiencies and shortcomings of the current stuck-at fault ATPG.