I(DDQ) testing of field programmable gate arrays

Abstract

Field Programmable Gate Arrays (FPGAS) represent an exciting technology that is changing the way logic circuits are designed. It is not until recently that testing of FPGA chips has received considerable attention. Research in testing of FPGAs has been focused on using the traditional stuck-at fault model. However, recently it has been shown that this model is inadequate as bridging faults play a dominant role in CMOS technology. The objective of this research is to develop an IDDQ-based test strategy for de tecting bridging faults in the logic and routing resources of FPGAS. The proposed approach utilizes the programmability and modularity of the FPGAs to achieve 100% fault detection Of IDDQ testable faults. As the programming time of an FPGA is significantly larger than the test time, then the lower speed Of IDDQ testing compared to a traditional voltage-based test approach is no longer a limitation. Also, as fault propagation is not required for observabiety, then the programming phases and test vectors needed are significantly less than for a voltage-based testing technique. All components in the FPGA chip except the configuration logic are considered. The resources consist of three parts: configurable logic blocks (CLBs), input/output blocks (IOBs), and routing resources including switch blocks (S blocks), connection blocks (C blocks), and peripheral switch blocks (PSBs). The proposed test strategy utilizes the homogeneous nature of an FPGA. The CLBS, S blocks and C blocks are axranged in a two-dimensional array. They are tested simultaneously; therefore, the whole array can be tested in a constant number of phases and test vectors, regardless of the array size. The I/O resources are also tested in parallel. The proposed IDDQ approach provides the advantages of significantly reduced testing time and high fault coverage.