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Bridging faults in CMOS circuits which are non-Iddq testable and their effect on delay testing
dc.creator | Tu, Gao | |
dc.date.accessioned | 2012-06-07T22:50:55Z | |
dc.date.available | 2012-06-07T22:50:55Z | |
dc.date.created | 1997 | |
dc.date.issued | 1997 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/ETD-TAMU-1997-THESIS-T8 | |
dc.description | Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item. | en |
dc.description | Includes bibliographical references: p. 36-38. | en |
dc.description | Issued also on microfiche from Lange Micrographics. | en |
dc.description.abstract | Bridging defects which occur in CMOS complementary gates (rather than ratioed logic gates) are investigated. Realistic bridging defects are shown to exist which are non-Iddq testable, but which can be deterministically tested using at speed voltage domain (logic) tests. Also. bridging faults are shown to be the cause of significant transition delay increases and decreases, therefore they can easily create new critical paths through the circuit. Finally, time domain testing and timing consideration for at speed voltage domain tests are discussed and compared with other testing methods. SPICE level 3 simulations using a technology file provided by Hewlett Packard have verified the observations made in this thesis. | en |
dc.format.medium | electronic | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en_US | |
dc.publisher | Texas A&M University | |
dc.rights | This thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use. | en |
dc.subject | electrical engineering. | en |
dc.subject | Major electrical engineering. | en |
dc.title | Bridging faults in CMOS circuits which are non-Iddq testable and their effect on delay testing | en |
dc.type | Thesis | en |
thesis.degree.discipline | electrical engineering | en |
thesis.degree.name | M.S. | en |
thesis.degree.level | Masters | en |
dc.type.genre | thesis | en |
dc.type.material | text | en |
dc.format.digitalOrigin | reformatted digital | en |
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