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Design and optimization of a defect tolerant processor array
| dc.creator | Lakkapragada, Bhavani S | |
| dc.date.accessioned | 2012-06-07T22:41:15Z | |
| dc.date.available | 2012-06-07T22:41:15Z | |
| dc.date.created | 1995 | |
| dc.date.issued | 1995 | |
| dc.identifier.uri | https://hdl.handle.net/1969.1/ETD-TAMU-1995-THESIS-L353 | |
| dc.description | Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item. | en |
| dc.description | Includes bibliographical references. | en |
| dc.description | Issued also on microfiche from Lange Micrographics. | en |
| dc.description.abstract | In this thesis we design and optimization of a defect tolerant MIMD processor array, for maximum performance per wafer area, targeted at applications that have a large number of operations per memory word, is described. The optimization includes trade-offs between number of processors, amount of local memory, performance and topology of the interconnection network and yield by way of evaluating the performance for each parallel application. Yield analysis is done on the reconfiguration architecture. The yield analysis considers the use of partially good cells to increase harvest rates. Keywords:Parallel Processing, Defect Tolerance, MIMD, Reconfiguration. | en |
| dc.format.medium | electronic | en |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en_US | |
| dc.publisher | Texas A&M University | |
| dc.rights | This thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use. | en |
| dc.subject | electrical engineering. | en |
| dc.subject | Major electrical engineering. | en |
| dc.title | Design and optimization of a defect tolerant processor array | en |
| dc.type | Thesis | en |
| thesis.degree.discipline | electrical engineering | en |
| thesis.degree.name | M.S. | en |
| thesis.degree.level | Masters | en |
| dc.type.genre | thesis | en |
| dc.type.material | text | en |
| dc.format.digitalOrigin | reformatted digital | en |
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