Abstract
Over the past five decades, electronic computers have gone through five generations of development. Each generation is distinguished by the tremendous improvement in performance over its predecessors. The improvements are mostly attributed to the increase in the chip and memory transistor density. Now, chip density and complexity are approaching their physical limits due to limitations imposed by the speed of light. This has prompted interset in scaling system resources by the number of processors used, and enlarging memory capacity. Scalable architectures delivering a sustained performance are desired in both sequential and parallel computers. However, parallel computers having a higher potential to deliver scalable performance are poised to become the new generation of electronic computers. The processing element architecture of this thesis is a unique combination of new computer generation concepts and early computers simplicity. This is a desirable combination of techniques and architecture for a processing element designed to be used in scalable massively parallel systems where it is advantageous to reduce space and power needs without sacrificing independent processor operation. The research that was conducted includes the design and development of a bitserial processing element and its associated on-chip memory. The goal of this design effort was to obtain a stand-alone processor with communication capabilities using a minimum number of instructions and a small instruction and data memory suitable for Fine-grain computing. The processing element has a two-phase clocking scheme where each clock can run at 40 MHZ. The processing chip is setup to be programmed to a Field Programmable Gate Array (FPGA) device using Altera programming software. The minimum requirement for the FPGA device is 56 input/output pins with a maximum 25ns delay and a 65 mm floorplan size.
Haidar, Faisal A (1994). Bit-serial RISC processing element for parallel processing. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1994 -THESIS -H1493.