A hybrid methodology for built-in self test

Abstract

A hybrid methodology for Built-In Self Test is presented. A method of designing a test pattern generator for Built-In Self Test is proposed which can generate both deterministic as well as pseudo-random patterns. This is accomplished with a single Linear Feedback Shift Register based generator, which automatically changes modes from deterministic to pseudo-random with no added control logic. One application of this method is illustrated where deterministic at-speed testing of C-testable Iterative Logic Arrays, covering all possible single and multiple combinational faults is achieved. Response Analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of Built-In Self Testing hardware are explained. Results, of applying the proposed test pattern generator on benchmark circuits show up to two orders of magnitude reduction in test length using this hybrid approach compared to pseudo-random Built-In Self Test using Linear Feedback Shift Registers.