Abstract
A Multithreaded instruction cache design for a Superscalar architecture supporting the concurrent execution of multiple independent instruction streams, termed as Hyperscalar is presented. The Hyperscalar architecture enhances the instruction issue rate by providing multiple functional units and improves resource utilization by supporting multiple instruction threads. The cache is lock up free, and is able to accept multiple requests which are stored in an input request queue. The cache can simultaneously resolve a miss generated by one instruction thread while satisfying a request for another instruction thread. The cache is set associative and is shared between the threads. A simulation model is developed to evaluate and compare the performance of the cache using trace driven simulations. Simulation results show a small cache can support two to four threads. A BICMOS circuit level implementation of the read access path in a typical set associative cache is used to estimate the average cache access time.
Rajagopal, Arjun (1993). Design of a multithreaded instruction cache for a hyperscalar processor. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1993 -THESIS -R1613.