Abstract
The microelectronic implementation of neural networks has received widespread attention over the last few years. However, the scale of the integration is still far below what microelectronics routinely offers in the traditional applications. The main reason is that most current techniques applied to neural networks lack space-power efficiency. The schemes proposed up to now mostly utilize transconductance-based circuits which often operate with high power consumption and some have complicated configurations. In this dissertation, the charge-based neural network circuits are explored as efficient alternatives for neural network hardware implementation. A binary-weight programmable Hamming network and an on-chip adaptation Kohonen neural network were designed, fabricated, and tested. They consist of several basic cell circuits such as the capacitive binary comparator, the charge-based analog comparator, the adaptive weight memory and the multiport charge sensing amplifier. They offer a significant advantage of high power-space efficiency over conventional approaches. The experimental results from CM O S chip-prototypes show the robust retrieval of patterns and the proper operation of unsupervised learning and classification functions.
He, Yuping (1992). The charge-based microelectronic implementation of neural networks. Texas A&M University. Texas A&M University. Libraries. Available electronically from
https : / /hdl .handle .net /1969 .1 /DISSERTATIONS -1468073.