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dc.creatorGunnam, Kiran Kumar
dc.creatorChoi, Gwan S.
dc.date.accessioned2022-08-31T19:00:44Z
dc.date.available2022-08-31T19:00:44Z
dc.date.issued6/21/2022
dc.identifier.urihttps://hdl.handle.net/1969.1/196772
dc.description.abstractA method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.en
dc.languageEN
dc.publisherUnited States. Patent and Trademark Officeen
dc.rightsPublic Domain (No copyright - United States)en
dc.rights.urihttp://rightsstatements.org/vocab/NoC-US/1.0/
dc.titleLow Density Parity Check Decoderen
dc.typeUtility patenten
dc.format.digitalOriginreformatted digitalen
dc.description.countryUS
dc.contributor.assigneeTexas A&M University Systemen
dc.identifier.patentapplicationnumber17/084564
dc.date.filed10/29/2020
dc.publisher.digitalTexas A&M University. Librariesen
dc.subject.cpcprimaryH03M 13/1177
dc.subject.cpcprimaryH03M 13/1128
dc.subject.cpcprimaryH03M 13/13
dc.subject.cpcprimaryH03M 13/116
dc.subject.cpcprimaryH03M 13/1105
dc.subject.cpcprimaryH03M 13/616


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