Now showing items 1-18 of 18

    • Algorithms for the scaling toward nanometer VLSI physical synthesis 

      Sze, Chin Ngai (Texas A&M University, 2007-04-25)
      Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip - these are just ...
    • Analytical Layer Planning for Nanometer VLSI Designs 

      Chang, Chi-Yu (2012-10-19)
      In this thesis, we proposed an intermediate sub-process between placement and routing stage in physical design. The algorithm is for generating layer guidance for post-placement optimization technique especially buffer ...
    • Case studies on lithography-friendly vlsi circuit layout 

      Shah, Pratik Jitendra (2009-05-15)
      Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength ...
    • Data integrity for on-chip interconnects 

      Singhal, Rohit (Texas A&M University, 2007-09-17)
      With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. ...
    • Design for manufacturing (DFM) in submicron VLSI design 

      Cao, Ke (2009-05-15)
      As VLSI technology scales to 65nm and below, traditional communication between design and manufacturing becomes more and more inadequate. Gone are the days when designers simply pass the design GDSII file to the foundry and ...
    • Efficient Design and Clocking for a Network-on-Chip 

      Mandal, Ayan (2013-05-02)
      As VLSI fabrication technology scales, an increasing number of processing elements (cores) on a chip makes on-chip communication a new performance bottleneck. The Network-on-Chip (NoC) paradigm has emerged as an efficient ...
    • An efficient logic fault diagnosis framework based on effect-cause approach 

      Wu, Lei (2009-05-15)
      Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit ...
    • High throughput low power decoder architectures for low density parity check codes 

      Selvarathinam, Anand Manivannan (Texas A&M University, 2005-11-01)
      A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design ...
    • IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION 

      Esquit Hernandez, Carlos A. (2010-01-16)
      Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied ...
    • An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization 

      Huang, Yi-Le (2012-02-14)
      Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and power optimization. Lagrangian relaxation (LR) is a common ...
    • Layout optimization in ultra deep submicron VLSI design 

      Wu, Di (Texas A&M University, 2006-08-16)
      As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several ...
    • Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling 

      Wang, Weihuang (2009-05-15)
      This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a ...
    • Minimizing and exploiting leakage in VLSI 

      Jayakumar, Nikhil (2009-05-15)
      Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has ...
    • Modeling, Design and Optimization of IC Power Delivery with On-Chip Regulation 

      Lai, Suming (2014-12-11)
      As IC technology continues to follow the Moore’s Law, IC designers have been constantly challenged with power delivery issues. While useful power must be reliably delivered to the on-die functional circuits to fulfill the ...
    • Performance and power optimization in VLSI physical design 

      Jiang, Zhanyuan (2009-05-15)
      As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...
    • Performance and power optimization in VLSI physical design 

      Jiang, Zhanyuan (Texas A&M University, 2008-10-10)
      As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic ...
    • Track Assignment Considering Crosstalk-Induced Performance Degradation 

      Zhao, Qiong (2012-07-16)
      Track assignment is a critical step between global routing and detailed routing in modern VLSI chip designs. It greatly affects some very important design characteristics, such as routability, via usage and timing performance. ...
    • VLSI Implementation of Low Power Reconfigurable MIMO Detector 

      Dash, Rajballav (2009-12-02)
      Multiple Input Multiple Output (MIMO) systems are a key technology for next generation high speed wireless communication standards like 802.11n, WiMax etc. MIMO enables spatial multiplexing to increase channel bandwidth ...