Abstract
Large scale multiprocessors are built on a particular interconnection network with a fixed number of processors. The interconnections are based on topologies like mesh, hypercube, etc. If the logical domain of a problem does not map to the physical configuration of the system, configuration must take place to map their domains. Building a parallel system is very expensive, and hence, we need solutions which allow to solve such problems on existing systems instead of designing a whole new system. The topology defined by processors and their interconnections has a major influence on cost and performance. Different embeddings exist for mapping their configurations. In this thesis, embeddings are analyzed using real applications on a mesh interconnection network. Three different embeddings techniques are presented. Performance analysis of embedclings with different logical configurations and comparison of the results with the original mesh interconnection network are discussed. Execution times of various applications (with and without the embeddings) are obtained through an execution driven simulation. The embeddings are shown to provide similar performance to the original mesh when the rectangular grid's height-width ratio is closer to unity. However, it is also shown that performance of the embeddings in all other cases doesn't differ significantly from the original mesh. However, the height-width ratio of the rectangular grid affects the average message latency and the read and the write stall times for all applications.
Krishnamoorthy, Deviusha (1997). Performance evaluation of configurable arrays with mesh interconnections and wormhole routing. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1997 -THESIS -K74.