dc.contributor.advisor | Choi, Gwan | |
dc.creator | Wang, Weihuang | |
dc.date.accessioned | 2010-01-15T00:08:17Z | |
dc.date.accessioned | 2010-01-16T00:37:29Z | |
dc.date.available | 2010-01-15T00:08:17Z | |
dc.date.available | 2010-01-16T00:37:29Z | |
dc.date.created | 2007-12 | |
dc.date.issued | 2009-05-15 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/ETD-TAMU-2504 | |
dc.description.abstract | This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading
channels and general AWGN channels. A model of a memory-efficient low-power
high-throughput multi-rate array LDPC decoder as well as its FPGA implementa-
tion results is first presented. Then, I propose a decoding scheme that provides the
feature of constant-time decoding and thus facilitates real-time applications where
guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The
results are then used to dynamically adjust decoder frequency and switch between
multiple-voltage levels; thereby energy use is minimized. This is in contrast to the
conventional fixed-iteration decoding schemes that operate at a fixed voltage level
regardless of the quality of data received. Analysis shows that the proposed decoding
scheme is widely applicable for both two-phase message-passing (TPMP) decoding
algorithm and turbo decoding message passing (TDMP) decoding algorithm in block
fading channels, and it is independent of the specific LDPC decoder architecture. A
decoder architecture utilizing our recently published multi-rate decoding architecture
for general AWGN channels is also presented. The result of this thesis is a decoder
design scheme that provides a judicious trade-off between power consumption and
coding gain. | en |
dc.format.medium | electronic | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en_US | |
dc.subject | VLSI | en |
dc.subject | LDPC | en |
dc.subject | low power | en |
dc.title | Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling | en |
dc.type | Book | en |
dc.type | Thesis | en |
thesis.degree.department | Electrical and Computer Engineering | en |
thesis.degree.discipline | Electrical Engineering | en |
thesis.degree.grantor | Texas A&M University | en |
thesis.degree.name | Master of Science | en |
thesis.degree.level | Masters | en |
dc.contributor.committeeMember | Chamberland, Jean-Francois | |
dc.contributor.committeeMember | Reddy, A. L. Narasimha | |
dc.contributor.committeeMember | Walker, Duncan M. | |
dc.type.genre | Electronic Thesis | en |
dc.type.material | text | en |
dc.format.digitalOrigin | born digital | en |