| dc.description.abstract | Ultra-wideband technology (UWB) has received tremendous attention since the
FCC license release in 2002, which expedited the research and development of UWB
technologies on consumer products. The applications of UWB range from ground
penetrating radar, distance sensor, through wall radar to high speed, short distance
communications. The CMOS integrated circuit is an attractive, low cost approach for
implementing UWB technology. The improving cut-off frequency of the transistor in
CMOS process makes the CMOS circuit capable of handling signal at multi-giga herz.
However, some design challenges still remain to be solved. Unlike regular narrow band
signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results
in the occupancy of wide frequency range. This demands that UWB front-end circuits
deliver both time domain and frequency domain signal processing over broad bandwidth.
Witnessing these technique challenges, this dissertation aims at designing novel, high
performance components for UWB signal generation, down-conversion, as well as
accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to
facilitate the discrete feature of the UWB signal. The transmitter employs novel twostage
-switching to generate carrier based UWB signal. The structure not only minimizes
the current consumption but also eliminates the use of a UWB power amplifier. The
fabricated transmitter is capable of delivering tunable UWB signal over the complete
3.1GHz -10.6GHz UWB band. By applying the similar two-stage switching approach,
we were able to implement a novel switched-LNA based UWB sampling receiver frontend.
The proposed front-end has significantly lower power consumption compared to
previously published design while keep relatively high gain and low noise at the same
time. The designed sampling mixer shows unprecedented performance of 9-12dB voltage
conversion gain, 16-25dB noise figure, and power consumption of only 21.6mW(with
buffer) and 11.7mW(without buffer) across dc to 3.5GHz with 100M-Hz sampling
frequency.
The implementation of a precise delay generator is also presented in the
dissertation. It relies on an external reference clock to provide accurate timing against
process, supply voltage and temperature variation through a negative feedback loop. The
delay generator prototype has been verified having digital programmability and tunable
delay step resolution. The relative delay shift from desired value is limited to within
0.2%. | en |
