Stuck-at-fault test set compaction

Abstract

Proper testing of manufactured digital circuits is critical to ensuring the number of defective parts is minimized. Automated test pattern generation tools are created in order to produce test patterns that can be applied with the intention of identifying as many defective parts as possible. The increasing complexity of digital circuit designs causes this task to continue to increase in difficulty. At the same time, the amount of time dedicated to testing should be kept constant. Therefore, it is crucial to limit the number of test patterns that are applied to any given circuit. Additionally, tester memories may limit the number of test patterns that may be applied at one time. This research demonstrates several existing methods of compaction and introduces a new method for measuring the contribution of each test pattern. Both static and dynamic compaction methods were implemented and evaluated in terms of final test pattern set size and diversity of excitation. The program resulting from this research has been shown to equal or surpass an existing automated test pattern generation tool.