Abstract
Limitations in processing ability cause major graphical enhancements, such as support for real-time 3D graphics, to be next to impossible within embedded devices. Due to the size, power, and heat dissipation requirements, modern graphics hardware is usually restricted to systems on the scale of personal computers or larger. For this thesis, we have defined a 3D graphics co-processor that is targeted to work on a more embedded scale. The system is specified by limiting it to fixed-point light processing and rasterization. A set of object primitives and instructions are defined to adequately describe almost any scene. These primitives are used to design the algorithms and architecture behind a set of modular functional units. The units are used to realize the processor requirements and features, which include light processing, z-buffering, texturing, and transparency. In order to ensure that the system architecture is versatile in its design, the functional units are analyzed for performance, reconfigurability, and possible trade-offs. A set of both synchronous and asynchronous architectures are proposed using the functional unit blocks. Through cycle accurate comparative simulation, we analyzed the effectiveness of each architecture and found that a hybrid architecture provides the best hardware to speed trade-off between the architectures considered. An appropriate system interface and parallel configuration are also discussed. The end result of the thesis provides a road map for anyone designing a general purpose or application optimized embedded 3D co-processor.
Murray, Brian (2002). Development of an embedded 3D graphics processor. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -2002 -THESIS -M87.