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A 1.8V 2-2 cascade Sigma-Delta modulator for high speed applications
|dc.description||Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to firstname.lastname@example.org, referencing the URI of the item.||en|
|dc.description||Includes bibliographical references (leaves 79-82).||en|
|dc.description||Issued also on microfiche from Lange Micrographics.||en|
|dc.description.abstract||In order to satisfy today's most important requirements of the A/D and D/A converters that are low voltage and high speed operation, a low voltage and high speed circuit solutions for  modulators are strongly demanding. However, simply reducing the supply voltage and increasing the clock frequency of the  modulator will introduce severe constraints to the design. In this thesis, a 1.8V 2-2 cascade  modulator with 1MHz signal bandwidth is realized by employing a modified  modulator structure which can limit the output swing of the integrator within half the reference voltage. As a result, the supply voltage can be easily reduced without any degradation of the modulator performance. Moreover, the slew rate and bandwidth requirements of the OpAmp are much more alleviated. Also, using only single bit quantizers in each stage, linearity and matching problems are not critical. Circuit level simulation results show a peak SNR of 77.3dB and a peak SNDR of 72.1dB which corresponds to a nearly 13 bit resolution.||en|
|dc.publisher||Texas A&M University|
|dc.rights||This thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.||en|
|dc.subject||Major electrical engineering.||en|
|dc.title||A 1.8V 2-2 cascade Sigma-Delta modulator for high speed applications||en|
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