Generation of RTL verification input stimulus

Abstract

This thesis presents an approach for generating input stimulus for verification of register-transfer level (RTL) design of VLSI circuits. RTL design is often subjected to a significant verification effort due to errors introduced during manual intervention. Simulation is widely used for verifying RTL designs despite its limitation. For a given coverage metric, the verification input vectors are generated to attain a higher level of coverage. Many verification coverage measures were proposed in the past that include code and branch coverage. Their limitations led to coverage based on control path. However, control based coverage provides good verification quality. Recent control based coverage approaches such as Extended Condition Coverage (ECC) provide better coverage quality through condition variable excitation and observation. The purpose of this research is to generate input stimulus for verification, based on ECC. The input stimulus is generated through gate-level analysis. Conventional automatic test pattern generation (ATPG) tools generate input vectors for the gate-level design. The proposed approach maps the condition cases in the RTL design to the gate-level stuck-at-faults. These stuck-at-faults are included in the fault list that guides the ATPG tool to generate input vectors for the gate-level design. These input vectors are sorted and re-mapped to generate verification input stimulus for the RTL design.