Accurate resistive bridge fault modeling, simulation, and test generation

Abstract

Resistive bridging faults in CMOS combinational circuits are studied in this work. Bridging faults are modeled using HSPICE circuit simulation of the various types of bridging faults that can occur in CMOS combinational circuits. The results of the circuit simulations are used to build look-up tables that contain data to be used at the fault site during voltage-based fault simulation and voltage test generation. Considering resistive bridges instead of zero-ohm bridges gives a fairly accurate description of the behavior of realistic bridging faults. Bridging fault simulation is done using different test sets in order to study the effectiveness of these test sets under resistive bridging fault conditions. An Automatic Test Pattern Generator (ATPG) for resistive bridging faults has been developed using this accurate fault model. The ATPG attempts to generate a test set that can detect the highest possible bridging resistance for each fault. The effect of lowering the power supply voltage on bridging fault detection is also studied, and some cases which lead to unusual behavior at reduced power supply voltage are presented. A comparison between a zero-ohm bridging fault model and the resistive bridging fault model developed is also made with the aim of determining the usefulness of the more complex resistive bridging fault model.