Testing dynamically reconfigurable FPGAs

Abstract

In this work, testing methods are proposed to test the ics. logic resources and the interconnect structure of dynamically reconfigurable FPGAS. Testing methods are also proposed for testing the dedicated CPU interface in these FPGAS. A BIST methodology is employed for testing the logic resources of the dynamically reconfigurable FPGA; this is coupled with system level diagnosis procedures to achieve detection and diagnosis of faults. The PMC model is applied to each hierarchical block in the FPGA. Configurations and tests are proposed which allow the diagnosis of t faulty modules in any hierarchical block. In each phase, some modules are configured to generate test vectors and other modules are tested. Dynamic and partial reconfiguration is used extensively to configure the same logic resources with different test generator circuits. The output responses of the tested modules to the applied test vectors are read through the CPU interface. A single stuck-at fault model is used to model faults in these modules. The expression for the maximal value of the diagnosability t, which depends upon the number of logic resources available in each hierarchical block, is derived. The interconnect structure is tested using a bottom-up approach. The interconnect resources in each direction are tested one by one. The interconnect resources at the lowest level of hierarchy (local interconnect) will be initially tested. A single stuck-at fault model is used for the local interconnect. Next, interconnect lines in different hierarchical levels are tested. A pair of interconnect lines in each row or column are tested in all phases for stuck-at and bridging faults. A "Walking-1s'' test sequence is used for fault detection in each case. In addition to the walking-1 test set an "All-0'' test vector is used to enable proper diagnosis of the modeled faults. All test vectors are generated by the logic resources in the FPGA and the output responses to these vectors are read via the dedicated CPU interface. The CPU interface is tested for stuck-at faults and addressing faults. In this case also, test vectors are generated by the logic resources in the FPGA.