Improving the accuracy of SRAM-based failure analysis using IDDQ testing

Abstract

is a primary means of identifying defects in semiconductor manufacturing processes. Defect monitoring is most often done by conventional voltage tasting, but voltage measurements do not always provide a unique mapping into defect characteristics. Quiescent power supply (IDDQ) current measurement can be used to improve diagnosability and categorizing the measured current level can provide a more accurate mapping from circuit failure to defect causes. The primary objective of this thesis is to increase the accuracy of SRAM-based defect diagnosis using calibrated IDDQ testing by including mode realistic bridging resistance distributions, and taking open defects into consideration. The outcome is better sampling efficiency, by predicting the likely defect type before a chip/wafer goes through physical Faille Analysis (FA). This is especially important when doing FA with Focused Ion Beam (FlB) to strip the chip layer by layer because knowing the defect layer reduces the analysis time.