Combinational logic optimization for low power using implication-based transformations

Abstract

The demand for portable equipment has increased the emphasis on low-power designs. Higher power consumption results in shorter battery-lifetime of portable electronic devices. As a result larger batteries are required for a reasonable operational time and this reduces the portability of the devices. There are several techniques which reduce power consumption during design of a it. This work presents one such technique which is applicable to a gate-level design. A combinational logic optimizer, Minpower, which reduces power consumption is presented. Heuristics and methods which help in guiding the optimization procedure towards a circuit with minimal power cost will be presented. Finally, experimental results on the ISCAS85 benchmark set and a comparision with various other techniques will be presented to demonstrate the effectiveness of the proposed technique.