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dc.creatorPastor, Curtis Lemay
dc.date.accessioned2012-06-07T22:50:03Z
dc.date.available2012-06-07T22:50:03Z
dc.date.created1997
dc.date.issued1997
dc.identifier.urihttps://hdl.handle.net/1969.1/ETD-TAMU-1997-THESIS-P378
dc.descriptionDue to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.en
dc.descriptionIncludes bibliographical references: p. 137-138.en
dc.descriptionIssued also on microfiche from Lange Micrographics.en
dc.description.abstract.This thesis addresses some of the problems encountered in Statistical Design of Analog Integrated Circuits (ICs). The objective is to develop a methodology to optimize an industrial operational amplifier (OpAmp) for improved performance and reduced variability based upon a statistical device model which expresses individual MOSFET behavior as a function of random process variables or noise parameters. The adopted methodology should be general enough to accommodate other complex analog circuits. However, development of an all-inclusive methodology is impractical and beyond the scope of this research. Once optimized, the circuit will then be manufactured, tested, and compared with the nominal circuit. Finally, it will be shown that the optimization methodology indeed produces improved performances and reduced circuit variability in accordance with the models and simulations performed prior to manufacture. Throughout this research, several obstacles were overcome to yield the final outcome. The steps taken in this research are briefly highlighted as follows: 1.Optimization of the nominal circuit under its original process to determine trade-offs inherent to the design, and feasibility of optimization. 2.Migration to a new process to facilitate fabrication at a later date. This involved the creation of a statistical device model (SDM) to accurately represent MOSFETs both physically and statistically under this process. 3.Optimizations of the circuit under the new process using the new SDM. 4.Layout of the circuits, both nominal and optimized, within the Cadence Design Framework II (TM) [1] environment using the MOSIS Design Kit (TM) [2]. 5.Fabrication and packaging of the circuits by MOSIS. 6. Testing of the circuits' performance. The Design for Quality and Manufacturability (DFQM) CAD tools, and other software tools used to implement this research are as follows: 1.GOSSIP[3]: A Generic System for Statistical Improvement of Performance, developed at the Electrical Engineering Department, Texas A&M University. 2.simvis95[4]: a utility program for visualization of statistical optimization data. 3.spectre[5]: Cadence's circuit simulator. 4. artil[l]: Cadence's post-processing tool. The application of these tools will be demonstrated in this thesis as the optimization methodology is described. Furthermore, certain assumptions will be made along the way which will be noted and discussed.en
dc.format.mediumelectronicen
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherTexas A&M University
dc.rightsThis thesis was part of a retrospective digitization project authorized by the Texas A&M University Libraries in 2008. Copyright remains vested with the author(s). It is the user's responsibility to secure permission from the copyright holder(s) for re-use of the work beyond the provision of Fair Use.en
dc.subjectelectrical engineering.en
dc.subjectMajor electrical engineering.en
dc.titleA statistical optimization methodology for practical integrated circuit design for quality and manufacturabilityen
dc.typeThesisen
thesis.degree.disciplineelectrical engineeringen
thesis.degree.nameM.S.en
thesis.degree.levelMastersen
dc.type.genrethesisen
dc.type.materialtexten
dc.format.digitalOriginreformatted digitalen


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