A 1.8V 10-bit 10MS/sec pipelined ADC

Abstract

The objective of this thesis is to develop a pipelined analog-to-digital converter which operates under a single supply voltage of 1.8V and is capable of resolving 10 bits at a rate of IOMS/sec. Although the overall architecture of the developed pipelined converter is a general one at the system level, a family of new low-voltage building blocks is proposed. The amplifiers and comparators which are designed to perform interstage processing have high gain-bandwidth products and they are capable of operating at supply levels of less than the initial specification of 1.8V. To test the concepts used to design important blocks such as amplifiers and comparators, a chip prototype amplifier is fabricated in a 1.2nm standard CMOS process and is tested to be functional. The entire converter system is designed using a 0.5/,nm standard CMOS process and its layout is completed. A patent application is filed for the offset cancelation utilizing capacitive levelshift devices for single-ended amplifiers.