Timing analysis of logic=level digital circuits using uncertainty intervals

Abstract

Timing Analysis of Logic-Level Digital Circuits Using Competitive design of modem digital circuits requires high performance at reduced cost and time-to-market. Timing analysis is increasingly used to deal with the more aggressive timing constraints inherent in high performance designs and the increased complexity of current VLSI technology. Reliance on synthesis and modular design to reduce cost and time-to-market has resulted in increased occurrence of non-functional paths which must be dealt with during timing analysis. In this work, an incremental timing analysis procedure is developed. Several techniques are introduced to improve the implicit trimming of false paths during path generation. The use of Recursive Learning to find indirect conflicts during the path building is studied. Dynamic dominators are introduced and used to prevent the checking of multiple paths with equivalent constraints. The technique of forward trimming is developed to discover blocked paths early and guide the search toward the true longest path. These techniques are shown to improve the search process during the path building phase of the incremental path generation routine. In addition, an improved dynamic sensitization criteria is presented which incorporates the actual delay of circuit elements. The delay of the circuit elements is dependent on the manufacturing process parameters. A min/max delay model is used to incorporate these variations of delay into the sensitization criteria. An uncertainty interval is used to represent transitions in the circuit since the exact time of the transition is unknown. The performance of the implicit path elimination techniques and the improved dynamic sensitization criteria is demonstrated through experimental results on some combinational benchmark circuits.