Abstract
In a semiconductor industry, packaging of integrated circuit chips, product quality control and rapid problem diagnosis are very critical to economic success. The integrated circuit package makes up a large fraction of the total production cost, and has a major influence on product perfo rmance and reliability. Increasing the yield in package assembly influence on product perfo will reduce the effective manufacturing cost during assembly. Hence integrated circuit manufacturers try to improve yields to profitable levels in a short time frame and to maintain the yield once they are acheived. Yields can be substantially increased when one can identify the causes for yield loss. In this research a methodology to predict the yield for package assemblies has been developed and implemented. Sensitivity analysis was performed to isolate the factors that affected yield learning the most. The yield model was developed after performing case studies on the Tape Carrier Package at Intel Corporation, the Plastic Quad Flat Pack and the Ceramic Ball Grid Array at IBM, and the Plastic Ball Grid Array at Motorola. This model has been used as a management toot for making yield predictions, resource allocations, understanding operating practices and provide what-if analysis. We developed a nonlinear spreadsheet-based model and tuned it to the manufacturing line in each company. We demonstrated the use of these models in industry to accurately predict the yield based on a set of user inputs. We have experimentally validated our approach by comparing the predicted yield to the actual yield values obtained in the assembly line. We have also developed a quantitative yield model based on absolute metrics and compared the results to the qualitative model that we developed. This model demonstrated an improved fit as compared to the qualitative model. This model also exposes the sensitivities of factors that were not significant in the yield model built with the qualitative factors.
Balasubramaniam, Gaurishankar (1996). Yield learning model for integrated circuit package. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1996 -THESIS -B354.