Design and implementation of a large integrated crossbar switch for a 256 x 256 x 8 interconnection network

Abstract

Crossbar switches provide the maximum possible bandwidth and minimum possible latency of all interconnect structures. Due to the large area required for large switches, monolithic crossbars have usually been limited to 64 x 64 ports. But many applications such as shared memory multiprocessors, ATM switches and networks that carry visual information require high bandwidth and/or low latency to increase overall system performance. Large crossbar switches would be very useful in these applications. We propose a new design for a 256 x 256 port full crossbar switch for use in multiprocessor and telecommunications applications. The switch has a 50 Mbyte/sec bandwidth per port and a low message latency. Distributed arbitration is provided for output port contention. High packaging density, high speed, and I/O minimization are achieved through the use of a large area, defect-tolerant monolithic implementation in a 0.8 micron CMOS technology. The number of spare rows and columns in the switch matrix is determined by a detailed yield analysis. Index Terms-Crossbar switch 7 buffer, delay, interconnection networks, packet, clock cycle, arbitration, performance, priority, yield analysis, latch, decoder, packaging, ball grid array.