Design and analysis of instruction issue logic for hyperscaler processors

Abstract

A dynamic instruction scheduling mechanism developed is presented. The proposed mechanism works out a compromise between the processor throughput and resource utilization. The scheduling mechanism issues instructions out of order. Destination registers are renamed to avoid anti and output dependencies by dynamically assigning a tag during instruction decode. Instructions from multiple streams are fetched in to a central window to improve the processor throughput. A hyperscalar processor model developed to evaluate the scheme is presented. The model is capable of handling variable number of threads, functional units, window sizes, operand buses, write ports and the number of instructions fetched. The cost of the proposed scheme and another hyperscalar scheduling mechanism is estimated. The cost-performance ratio of the two schemes are analyzed. Simulation results show a substantial increase in the processor throughput and resource utilization when the proposed scheme is used.