Implementation of a Header Processor for the PSi architecture

Abstract

The fast development of optical communication technology in the past decade has brought forth the possibility of very high speed data transmission for computer networks. Fiber optic communucations offer a combination of high bandwidth, low error probability and gigabit transmission capacity. To take full advantage of the data transmission rates offered by a fiber optic medium, it is essential to have network processing components that can cope with these rates. The typical approach of using a software for protocol processing creates a lot of processing bottlenecks, thus reducing the throughput. The PSi layer processing architecture was proposed for the processing of protocols, which transforms the high level specifications of protocols into effcient and correct hardware layouts. A main component of this architecture is the Header Processor. A Header Processor was designed at the transistor level and fabricated to test the possibilities of having a processor that will run on a 50 MHz clock, based on a proposed architecture. Design, simulation and fabrication of this processor using 2 micron CMOS technology resulted in a processor that can run on a 2.35 MHz clock.