Design of a PSi header processor for the internet protocol

Abstract

With the progress of the fiber-optic and VLSI technologies, a network can offer increasing capability at decreasing error rate. But the ultimate throughput delivered to the user application has not increased as rapidly. The main performance bottleneck is the network transport component, i.e. the network I/O at the end system. To overcome this performance bottleneck, a standard data communication protocol, such as TCP/IP, could be implemented by using hardware to speedup the protocol throughput. The objective of this research is to design a PSi header processor which could be used to implement the internet protocol to achieve a throughput of 1 GigBits/Sec. The design is based on the PSi layer architecture, which has an advantage of paral lelism normally found inside the protocols. A RISC architecture for the PSi header processor will be presented in this thesis. The microprograms associated with the hardware architecture of the header processor are also developed. To verify the correctness of the design, the behavior of the header processor based on the proposed microprograms is simulated by using the Verilog HDL. It is concluded that the header processor is performing as it is designed. By using a 50 MHz clock rate, the RISC based header processor designed above has achieved a minimum throughput of 1 GigBits/Sec.