A hardware-based approach to adaptive load-sharing on a local area network

Abstract

Load-distribution is used to enhance the performance of distributed systems. Two types of load-distribution techniques have been studied and used: load-sharing schemes, in which the total load on the system is distributed in such a way that no machine is idle when runnable tasks are queued up for execution at another machine in the distributed system, and load-balancing schemes, which try to equalize the load on the entire system. Most existing load-distributing schemes communicate with a single node at a time. The scheme proposed here uses the broadcast nature of the Ethernet protocol to communicate with all the nodes on the network simultaneously. A load-sharing chip is proposed which reduces the overhead of packet processing on the CPU. This chip also aids a heavily-loaded processor in speeding up the process of finding a lightly-loaded partner on the network. The collisions on the Ethernet can be easily detected at the hardware level and thus by shifting the process of finding a lightly-loaded node to the physical layer (hardware), a more updated system state can be used for migrating the processes. This is particularly useful when two or more nodes are contending to migrate a process to the same lightly-loaded node. The nodes which experience a collision can retreat and find a new partner. A new hard-wired comparator for comparing 256 16-bit load vectors has been developed and simulated using the Hspice circuit simulator. The simulations showed a good delay performance. A Verilog HDL model for the load-sharing chip has been developed and the design was verified with extensive simulations. Keywords: Local Area Networks, Load-info packets, Load-sharing, Load-balancing, Lightly-loaded, Heavily-loaded, Verilog HDL, and Hspice.