Abstract
Recently, learning-based techniques have been proposed as an efficient alternative to the traditional branch-and-bound techniques for test generation. The learning techniques have been shown to be extremely effective in finding test vectors for hard to detect faults and in detecting redundant faults. Learning techniques have also been effectively applied to the problem of design verification for combinational circuits. This paper presents Functional Learning, a new method of learning, based on implication procedures using the binary decision diagrams (BDD) as the main data structure. This method is complete-given enough time, it will determine all the uniquely implied values in the circuit from the current situation of value assignments. The most attractive feature of Functional Learning is its ability to extract, maintain and manipulate novel information regarding the circuit in terms of compact BDD representations for Boolean functions. In this research, Functional Learning has been applied to the problems of combinational circuit ATPG and design verification for combinational logic circuits. The results obtained indicate that Functional Learning is indeed a very powerful tool for application to CAD problems.
Mukherjee, Rajarshim (1994). Application of functional learning to ATPG and design verification for combinational circuits. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1994 -THESIS -M953.