Design and simulation of an FPGA architecture

Abstract

This thesis investigates the design and simulation problems of application specific Field Programmable Cate Array (FPGA) architectures. As a revolutionary idea in semicustom integrated circuits, FPGAs can provide very low prototype and manufacturing costs. The main features of most of the commercially available FPGA chips and the FPGA architectures currently under investigation are summarized in the first two chapters of this thesis. The utilization of Digital Signal Processing(DSP) is increasing in many areas. General purpose FPGAs are not efficient for DSP applications where only a small class of logic functions are frequently used. A new FPGA architecture for DSP applications is proposed in this thesis. This architecture is called RAM-Based FPGA for DSP applications(RBFD). Static RAM programming technology is employed in the RBFD to provide the in-circuit re-programmability. The RBFD is implemented with CMOS and BICMOS technologies. Evaluation of this architecture is made by mapping DSP logic functions, the RBFD demonstrates a better speed performance and less area cost than general purpose FPGAs for DSP applications. The speed is increased up to 69% with two to five times less area cost compared with the Triptych FPGA and Xilinx 3000.