Buffer assignment algorithms for data driven architectures

Abstract

Data driven architectures designed to achieve high performance and throughput require the corresponding data flow graph to have no accumulation of data at its nodes and simultaneous arrival of all input data to a multi-input node. Buffers are therefore inserted to ensure these conditions. An algorithm for buffer distribution in a balanced Data Flow Graph, DFG is proposed. The number of buffers in the proposed buffer distribution strategy is equal to the minimum number of buffers as achieved by integer programming techniques. We also propose an extension of this algorithm which can further reduce the number of buffers by altering the DFG while keeping the functionality and performance of the DFG intact. The time complexities of the proposed algorithms have been shown to be O(V x E) and O(V'xlogV) re spectively; an improvement over the existing strategies. A novel buffer distribution algorithm to maximize the pipelining and throughput has also been proposed. The number of buffers obtained by this algorithm is substantially less than the existing schemes and can be effectively applied to data driven architectures with large node sizes. Performance results indicate that the proposed strategies outperform all the existing strategies in terms of the number of buffers, while possessing the lowest time complexities.